Modelling and Tuning

<..Back to Research and Development Program


Using a model it's showing there may be some overlapping issues at full frequency:



Improving the model (and learning the software better) leads to a quite useful model where the results
do see to be similar to measured values on the real circuit.

This means a bit of tweaking quickly shows results (without blowing expensive IGBTS too:).

So this is an equivalent circuit to get some usable results from the model:

In the model we put 50nF capacitors to represent the IGBT gates and we are looking at one high side and one low side.
Also the high side is connected to two inductors of the motor, which should be about 10mH each.

And we can see the results for a 48uS period - 4 "rotations" with a mark/space of 10uS/10uS (50kHz PWM):

Above is input and gate voltages, plus a trace on the high side emitter (see circuit above).


Above is input currents for low side IGBT.


Above is input currents for high side IGBT.

A current source was added as part the logic output for the gate drivers instead of R8/R10:


Original Qucs schematic | and Qucs graph data

These graphs show the currents supplied to the driver circuits:
Each transition graph spans 500nS:





These graphs above show gate voltage switching between about 1v and 18v in around 200-500nS so well within targets of 1uS.


This is the total transfer from logic to gate.

To complete the picture we should add the IGBTs but there is no model for these.
The primary concern for this model is the (dis)charging times of the gates.

These graphs are the various checks for component tolerances:


Graph 2 (from the top) is to see if the fake BLDC motor is doing something close to what is expected in the real motor.
This shows the high "emitter" is varying between about +250v spiking down to -600v with a current rising to over 700A in 48uS.
Whilst obviously not perfect, at least it is varying around some real life values.

Graphs 3 on are for power calculations for the components to ensure they are within tolerance.
  1. T8 which shows max < 1mA -see below (KSP94 625mW or ZTX758 1W)
  2. R18 which shows max 20mA at 5 v so 100mW (R18 1/8W)
  3. T17 max 310v at 20mA so 6W (BUL58D are 450V/85W)
  4. T8 max 310v at 1mA (from above) so 310mW (KSP94 400V/625mW or ZTX758 400V/1W)
  5. T9 max 310v at 10mA so 3.1W for 1uS then 0W for 10uS so average 310mW (KSP94 400V/625mW or ZTX758 400V/1W)
  6. T10 max 20v at 10mA so 200mW (ZTX658 400V/1W)

This is for a 50kHz PWM, which the controller will never reach.
All the power calculations are for worse than worse case, specifically in the driver circuit.


These graphs are to show the currents in the driver input circuits.

This graph shows 20mA at 20v on ZD1 gives 400mW (zener is 500mW) and there is +/-10mA spikes for gate driver bases.
There are +/-17A spikes on the gates (BUL58D peak 16A).
The high side is asymmetric due to the floating "emitter".

The spike on the BUL58D is excess of it's rated 16A max but only for about 10nS.
The BUL58D datasheet uses a "peak" rating duration of 5mS, so while briefly slightly above the max rating it should be OK.

So this model shows the circuit should easily hits the target of 1uS switch times and all components are within tolerance.
This does not add the real-life switch speeds of the various components, particularly T8 and T11.
In the real circuit are either KSP94 or ZTX758, but these seem to have a slow switch speed.
Using them as drivers to the high power fast switch BUL58B seems to improve the switching times of the circuits.

Taking a second look at the data it seems obvious now that neither the KSP94 nor ZTX758 are going to work.
They both have a turn off time in the 2-3uS range.
Apparently it's mainly due to the charge on the base which needs to discharge before it switches off

So the more research and some more simulation shows a solution.

Replacing the BUL58D and driver with a MOSFET and emitter follower pair to ensure fast gate charging:

Original Qucs schematic


Original Qucs Display
Above is the switch time of the logic side FET: gate is (dis)charging in under 50nS.


Original Qucs Display
Above is the IGBT gate switching: (dis)charge is under 300nS

Class-D Controller Modelling

SPICE

SPICE (wikipedia) is pretty much the industry standard for electronic simulation.

If you are thinking of purchasing a simulator you should know that the simulation engine will be most likely be SPICE,
which has been free (now BSD licenced) since it's first iteration in 1973.

The problem is that it's a bit of a clique: the users of SPICE don't really remember the first problems they had learning how to use SPICE, so...

First a real quick howto worked example:

Original gschem schematic

graham@gnorth-workstation:~/Desktop/Data/Projects/Work/Car/Electronics$ cat rc.sch
v 20130925 2
C 45700 44300 1 0 0 vsin-1.sym
{
T 46400 44950 5 10 1 1 0 0 1
refdes=V2
T 46400 45150 5 10 0 0 0 0 1
device=vsin
T 46400 44750 5 10 1 1 0 0 1
value=sin 1 1 50000kHz
T 45700 44300 5 10 0 0 0 0 7
comment=SIN(VO VA FREQ TD THETA)

VO (offset)	 		V or A
VA (amplitude)		V or A
FREQ (frequency)		1/TSTOP	Hz
TD (delay)			0.0	s
THETA (damping factor)	0.0	s-1
}
N 46000 45500 46000 46500 4
N 50000 43500 45000 43500 4
N 46000 44300 46000 43500 4
C 45400 43200 1 0 0 gnd-1.sym
N 45000 48500 50000 48500 4
C 46600 46400 1 0 0 resistor-2.sym
{
T 47000 46750 5 10 0 0 0 0 1
device=RESISTOR
T 46800 46700 5 10 1 1 0 0 1
refdes=R2
T 46800 46200 5 10 1 1 0 0 1
value=10k
}
N 46000 46500 46600 46500 4
{
T 46200 46500 5 10 1 1 0 0 1
netname=Vb
}
N 47500 47500 48300 47500 4
N 49000 46900 49000 45800 4
{
T 49000 46600 5 10 1 1 0 0 1
netname=emitters
}
N 49000 48100 49000 48500 4
C 45300 48500 1 0 0 12V-plus-1.sym
C 48300 46900 1 0 0 transistor.sym
{
T 49300 47700 5 8 0 0 0 0 1
device=NPN_TRANSISTOR
T 49300 47500 5 10 1 1 0 0 1
refdes=Q1
T 49300 47800 5 8 0 2 0 0 1
footprint=TO92
T 49300 47400 5 10 1 1 180 6 1
model-name=BC547B
T 48300 46900 5 10 0 0 0 0 1
model=BF=500 NE=1.3 ISE=9.72F IKF=80M IS=20F VAF=50 ikr=12m BR=10 NC=2 VAR=10 RB=280 RE=1 RC=40 VJE=.48 tr=.3u tf=.5n
}
C 48300 44600 1 0 0 transistor-pnp.sym
{
T 49300 45400 5 8 0 0 0 0 1
device=PNP_TRANSISTOR
T 49300 45200 5 10 1 1 0 0 1
refdes=Q2
T 49300 45500 5 8 0 2 0 0 1
footprint=TO92
T 49300 45000 5 10 1 1 180 6 1
model-name=BC557B
T 48300 44600 5 10 0 0 0 0 1
model=BF=335 NE=1.5 ISE=7.35F IKF=82M IS=10F VAF=40 ikr=12m nc=2 br=4 var=10 rb=280 re=1 rc=40 vje=.48 tf=.5n tr=.3u
}
N 49000 43500 49000 44600 4
N 47500 45200 48300 45200 4
{
T 47600 45300 5 10 1 1 0 0 1
netname=bases
}
N 47500 47500 47500 45200 4
C 45200 47000 1 0 0 vdc-1.sym
{
T 45900 47650 5 10 1 1 0 0 1
refdes=V1
T 45900 47850 5 10 0 0 0 0 1
device=VOLTAGE_SOURCE
T 45900 48050 5 10 0 0 0 0 1
footprint=none
T 45900 47450 5 10 1 1 0 0 1
value=DC 12V
}
N 45500 48200 45500 48500 4
N 45500 47000 45500 43500 4
graham@gnorth-workstation:~/Desktop/Data/Projects/Work/Car/Electronics$ gnetlist -vg spice-sdb -o rc.net rc.sch
Loading schematic [/home/graham/Desktop/Data/Projects/Work/Car/Electronics/rc.sch]


------------------------------------------------------
Verbose mode legend

n : Found net
C : Found component (staring to traverse component)
p : Found pin (starting to traverse pin / or examining pin)
P : Found end pin connection (end of this net)
R : Starting to rename a net
v : Found source attribute, traversing down
^ : Finished underlying source, going back up
u : Found a refdes which needs to be demangle
U : Found a connected_to refdes which needs to be demangle
------------------------------------------------------

- Starting internal netlist creation
 CpnnnPpnnnPnPnP CpnnnPnPnP CpnnnPnPpnnnP CpnnnPnP CpnnnPnPpnnPpnnnnPP CpnnPpnnnnPP
nPpnnnPnP CpnnnnPPpnnnnPPnP DONE

- Staring post processing
- Naming nets:
pnpnpnpnpnpnpnpnpnpnpnpnpnpn DONE
- Renaming nets:
 DONE
- Resolving hierarchy:
 DONE
 DONE

- Staring post processing
- Naming nets of graphical objects:
 DONE

Internal netlist representation:

component V2 
	pin 1 (+) Vb
		V2 1 [6]
		R2 1 [45]
	pin 2 (-) GND
		V2 2 [11]
		Q2 1 [113]
		V1 2 [158]

component SPECIAL 
	pin 1 (1) Null net name
		V2 2 [11]
		Q2 1 [113]
		V1 2 [158]

component R2 
	pin 2 (2) bases
		R2 2 [40]
		Q2 2 [123]
		Q1 2 [87]
	pin 1 (1) Vb
		R2 1 [45]
		V2 1 [6]

component SPECIAL 
	pin 1 (1) Null net name
		Q1 1 [72]
		V1 1 [153]

component Q1 
	pin 1 (C) +12V
		Q1 1 [72]
		V1 1 [153]
	pin 3 (E) emitters
		Q1 3 [77]
		Q2 3 [108]
	pin 2 (B) bases
		Q1 2 [87]
		Q2 2 [123]
		R2 2 [40]

component Q2 
	pin 3 (E) emitters
		Q2 3 [108]
		Q1 3 [77]
	pin 1 (C) GND
		Q2 1 [113]
		V2 2 [11]
		V1 2 [158]
	pin 2 (B) bases
		Q2 2 [123]
		R2 2 [40]
		Q1 2 [87]

component V1 
	pin 1 (+) +12V
		V1 1 [153]
		Q1 1 [72]
	pin 2 (-) GND
		V1 2 [158]
		V2 2 [11]
		Q2 1 [113]


Using SPICE backend by SDB -- Version of 4.28.2007
schematic-type = normal schematic
found normal type schematic
Make first pass through design and create list of all model files referenced.
Done creating file-info-list.

Now process the items in model file list -- stick appropriate references to models in output SPICE file.
Done processing items in model file list.
Make second pass through design and write out a SPICE card for each component found.
--- checking package = V1
    device = VOLTAGE_SOURCE
Found independent voltage source.  Refdes = V1
--- checking package = Q2
    device = PNP_TRANSISTOR
Found pnp bipolar transistor.  Refdes = Q2
Checking prefix.  Package prefix =Q
                  correct prefix =Q
   nomunge mode = #f
  different-prefix=#f
found model and model-name for Q2
--- checking package = Q1
    device = NPN_TRANSISTOR
Found npn bipolar transistor.  Refdes = Q1
Checking prefix.  Package prefix =Q
                  correct prefix =Q
   nomunge mode = #f
  different-prefix=#f
found model and model-name for Q1
--- checking package = R2
    device = RESISTOR
Found resistor.  Refdes = R2
--- checking package = V2
    device = vsin
Found independent voltage source.  Refdes = V2
Done writing SPICE cards . . .


Output file is written.  We are done.
graham@gnorth-workstation:~/Desktop/Data/Projects/Work/Car/Electronics$ cat rc.net 
* gnetlist -vg spice-sdb -o rc.net rc.sch
*********************************************************
* Spice file generated by gnetlist                      *
* spice-sdb version 4.28.2007 by SDB --                 *
* provides advanced spice netlisting capability.        *
* Documentation at http://www.brorson.com/gEDA/SPICE/   *
*********************************************************
*==============  Begin SPICE netlist of main design ============
V1 +12V 0 DC 12V
Q2 0 bases emitters BC557B 
.MODEL BC557B PNP (BF=335 NE=1.5 ISE=7.35F IKF=82M IS=10F VAF=40 ikr=12m nc=2 br=4 var=10 rb=280 re=1 rc=40 vje=.48 tf=.5n tr=.3u)
Q1 +12V bases emitters BC547B 
.MODEL BC547B NPN (BF=500 NE=1.3 ISE=9.72F IKF=80M IS=20F VAF=50 ikr=12m BR=10 NC=2 VAR=10 RB=280 RE=1 RC=40 VJE=.48 tr=.3u tf=.5n)
R2 Vb bases 10k  
V2 Vb 0 sin 1 1 50000kHz
.end
graham@gnorth-workstation:~/Desktop/Data/Projects/Work/Car/Electronics$ ngspice
******                                                                                      
** ngspice-24 : Circuit level simulation program                                            
** The U. C. Berkeley CAD Group                                                             
** Copyright 1985-1994, Regents of the University of California.                            
** Please get your ngspice manual from http://ngspice.sourceforge.net/docs.html             
** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html               
** Creation Date: Wed Apr 16 21:09:20 UTC 2014                                              
******                                                                                      
ngspice 2 -> source rc.net                                                                  
                                                                                            
Circuit: * gnetlist -vg spice-sdb -o rc.net rc.sch                                          

ngspice 2 -> tran 0.01ns 50ns
Doing analysis at TEMP = 27.000000 and TNOM = 27.000000

Warning: v1: no DC value, transient time 0 value used

Initial Transient Solution
--------------------------

Node                                   Voltage
----                                   -------
+12v                                        12
bases                                        1
emitters                               1.00377
vb                                           1
v1#branch                          9.00883e-12
v2#branch                         -2.30231e-11



No. of Data Rows : 5008
ngspice 2 -> plot emitters bases
Use right mouse button to select and zoom

ngspice 2 -> set color0=rgb:f/f/f
ngspice 2 -> set color1=rgb:0/0/0
ngspice 2 -> plot emitters bases

ngspice 2 -> set color1=#7F7F7F
ngspice 2 -> plot emitters bases

SPICE quirks

Since pins on components are passed to spice by the order in the model and not by any labels, the symbol needs to have its pins in the correct order.

Here a transistor has pin 1 collector, pin 2 base and pin 3 emitter, which is correct:

graham@gnorth-workstation:~/Desktop/Data/Projects/Work/Car/Electronics$ cat local/transistor-pnp.sym
v 20130925 2
P 700 1200 700 900 1 0 0
{
T 600 950 5 8 0 1 0 0 1
pinnumber=3
T 100 1250 5 8 0 0 0 0 1
pinseq=3
T 800 1000 9 8 1 1 0 0 1
pinlabel=E
T 100 1100 5 8 0 1 0 0 1
pintype=pas
}
P 700 300 700 0 1 0 1
{
T 600 150 5 8 0 1 0 0 1
pinnumber=1
T 900 50 5 8 0 0 0 0 1
pinseq=1
T 800 100 9 8 1 1 0 0 1
pinlabel=C
T 900 200 5 8 0 1 0 0 1
pintype=pas
}
V 600 601 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 1000 800 5 8 0 0 0 0 1
device=BC182
L 700 300 500 500 3 0 0 0 -1 -1
L 700 900 500 700 3 0 0 0 -1 -1
L 500 800 500 400 3 0 0 0 -1 -1
P 0 600 284 600 1 0 0
{
T 200 450 5 8 0 1 0 0 1
pinnumber=2
T 0 150 5 6 0 0 0 0 1
pinseq=2
T 100 700 9 8 1 1 0 0 1
pinlabel=B
T 0 300 5 8 0 1 0 0 1
pintype=pas
}
L 500 600 284 600 3 0 0 0 -1 -1
L 500 700 572 736 3 0 0 0 -1 -1
L 500 700 536 772 3 0 0 0 -1 -1
L 536 772 572 736 3 0 0 0 -1 -1
T 1000 600 8 10 1 1 0 0 1
refdes=Q?
T 1000 500 5 8 0 0 0 0 1
value=BC182
T 1000 900 5 8 0 0 0 0 1
footprint=TO92
T 1000 1100 5 8 0 0 0 0 1
numslots=0
T 1000 1000 5 8 0 0 0 0 1
description=Small Signal NPN Bipolar
T 1000 1200 5 8 0 0 0 0 1
documentation=http://www.onsemi.com/pub/Collateral/BC182-D.PDF

Also make sure the device has the correct attributes for DEVICE, MODEL-NAME and MODEL; or your netlist with not be right.

More information...

https://groups.google.com/forum/#!topic/sci.electronics.cad/lCglI_jKjz8
.model bc547a NPN BF=400 NE=1.3 ISE=10.3F IKF=50M IS=10F VAF=80 ikr=12m
       + BR=9.5 NC=2 VAR=10 RB=280 RE=1 RC=40 VJE=.48 tr=.3u tf=.5n
       +cje=12p vje=.48 mje=.5 cjc=6p vjc=.7 mjc:.33 isc=47p kf=2f
.model bc547b NPN BF=500 NE=1.3 ISE=9.72F IKF=80M IS=20F VAF=50 ikr=12m
       + BR=10 NC=2 VAR=10 RB=280 RE=1 RC=40 VJE=.48 tr=.3u tf=.5n
       +cje=12p vje=.48 mje=.5 cjc=6p vjc=.7 mjc:.33 isc=47p kf=2f
.model bc547c NPN BF=730 NE=1.4 ISE=29.5F IKF=80M IS=60F VAF=25 ikr=12m
       + BR=10 NC=2 VAR=10 RB=280 RE=1 RC=40 VJE=.48 tr=.3u tf=.5n
       +cje=12p vje=.48 mje=.5 cjc=6p vjc=.7 mjc:.33 isc=47.6p kf=2f
.model BC557a PNP BF=190 NE=1.5 ISE=12F IKF=90M IS=10F VAF=50 ikr=12m
       + nc=2 br=4 var=10 rb=280 re=1 rc=40 vje=.48 tf=.5n tr=.3u
       +cje=12p vje=.48 mje=.5 cjc=6p vjc=.7 mjc:.33 isc=47.6p kf=2f
.model BC557b PNP BF=335 NE=1.5 ISE=7.35F IKF=82M IS=10F VAF=40 ikr=12m
       + nc=2 br=4 var=10 rb=280 re=1 rc=40 vje=.48 tf=.5n tr=.3u
       +cje=12p vje=.48 mje=.5 cjc=6p vjc=.7 mjc:.33 isc=47.6p kf=2f
.model BC557c PNP BF=490 NE=1.5 ISE=12.4F IKF=78M IS=60F VAF=36 ikr=12m
       + nc=2 br=4 var=10 rb=280 re=1 rc=40 vje=.48 tf=.5n tr=.3u
       +cje=12p vje=.48 mje=.5 cjc=6p vjc=.7 mjc:.33 isc=47.6p kf=2f


Modelling the controller

As with QUCS the circuit for the model is different from the real circuit

So this is the model of the MCU side:

Original gschem schematic


Then the high voltage push-pull:

Original gschem schematic


And finally the single-ended output:

Original gschem schematic



So this is currently modelling the major parts and this is very close to what is seem in the real circuit.

The experience with SPICE is much better than QUCS.
A person can spend hours just trying to coax a single simulation out of QUCS having to mess with the parameters to remove the Jacobian Singulars.
Even then it could take a while to run a simulation.

SPICE, on the other hand, seems to pretty instantly work so long as there are no silly errors.
And the output from a broken simulation is quite useful in fixing bugs in the circuit.


Original gschem schematic




Original gschem schematic




Original gschem schematic




Original gschem schematic




Original gschem schematic